The present invention relates to an image signal processing apparatus for encoding an image signal into a code signal and decoding a code signal into an image signal at a high speed. More particularly, the invention relates to an image signal processing apparatus and an information transmission and reception apparatus for encoding a bit map image signal into a code signal and decoding a code signal into an image signal at a high speed.
In a facsimile apparatus for transmitting white-and-black binary image data, MH, MR, MMR encoding schemes are used to improve the transmission efficiency as recommended by CCITT (Consultative Committee in International Telegraphy and Telephony). Apparatuses of this type are, for example, M66330SP/FP disclosed in Mitsubishi Semiconductor Data Book and HD63185FS (DICEP-E) disclosed in the User Manual published by the semiconductor department of Hitachi Ltd.
If the number of transition points per unit length is large, the encoding speed lowers and the amount of encoded codes increases. When the number of transition points per unit length exceeds a certain limit, the amount of encoded codes exceeds the number of image data bits. A technique of reducing the amount of encoded codes is disclosed in JP-A-61-252765.
High speed image signal decoding systems for decoding an encoded image signal into an original image signal at a high speed are known as in the following.
In a xe2x80x9cplain paper laser facsimilexe2x80x9d described in the magazine Denshi Gijutsu,1990-8, a decoded image signal is stored in a page memory having a capacity of more than one page, and the stored image signal is outputted at a constant high speed to a laser printer.
In the Publication JP-A-59-126368, an encoded signal supplied via a system bus is decoded by accessing an image signal on a reference line stored in an image memory connected to an image bus. The decoded image signal is stored in the image memory and outputted to a printer.
In the article xe2x80x9cIntroduction of ASIC to High Speed Facsimilexe2x80x9d of the magazine Denshi Gijutsu, 1988-4, an encoded signal supplied via a system bus is decoded in real time. The decoded image signal is directly outputted to a laser printer without storing it in a page memory.
In the Publication JP-A-62-133865, an image signal of one page can be recorded on two pages and the same partial image can be recorded on both the bottom portion of the first page and the top portion of the second page, by switching between the input image signal and the image signal stored in the image memory.
It is an object of the present invention to provide an image signal processing apparatus and an information transmission and reception apparatus, capable of encoding an image signal into a code signal and decoding a code signal into an image signal to record it, at a high speed.
It is another object of the present invention to provide a high speed image signal processing apparatus and a high speed information transmission and reception apparatus capable of setting the input bit rate of an image signal at least to the coding operation speed while ensuring the reliable transmission and reception of a code signal.
According to one aspect of the present invention, there is provided an image signal processing apparatus comprising: encoding unit having a plurality of line memories for storing an input image signal, the encoding unit encoding the image signal into a code signal while always confirming that the image signal of at least one line is stored in the line memories; and decoding unit having a plurality of line memories for storing the decoded image signal, the decoding unit decoding an input code signal from a page intermediate position as well as one of a page top position.
The decoding unit is connected via an image bus to at least an image memory and a recording unit for recording the image signal, the image memory storing a decoded image signal of a plurality of lines.
The decoding unit includes at least a code analyzer, the plurality of line memories for storing the decoded image signal, a transition point calculator, an image signal recovering unit, a register group, a control sequencer, and a transfer unit, respectively connected to a bus, the code analyzer analyzing the code signal, the transition point calculator calculating a transition point of the code signal related image signal stored in one of the line memory, the image signal recovering unit recovering the image signal from the code signal related image signal at the area from an address one point before the transition point address and to the transition point address, the register groups storing at least the number of lines of the image signal and the transition point address, the control sequencer controlling the sequence of the decoding operation, and the transfer unit transferring the recovered image signal stored in one of the line memories to the image bus via an image bus interface.
The control sequencer includes at least an error detecting unit for detecting an error of the code signal related image signal and informing an error to the transfer unit.
The register group includes a decoded line umber storing register for storing the number of decoded lines of the image signal and a decoded line number managing register for updating the contents of the decoded line number storing register each time one line has been decoded. The decoded line number managing register initializes the contents of the decoded line number register when the decoding operation starts from the page top position, and does not initiate the contents when the decoding operation starts from the page intermediate position.
The register group includes an address register for storing an address of the image signal and a transfer line number register for storing the number of lines of the image signal to be outputted to the recording unit.
The register group includes a first position setting register for storing the position to forcibly change the decoded image into a white pixel signal when the image signal on the line with the error is outputted to the image memory and the recording unit, and a second position setting register for storing the position to forcibly change the decoded image into a black pixel signal when the image signal on the line with the error is outputted to the image memory and the recording unit.
The register group includes a first register for instructing addition of an error mark to the image signal on the line with the error, if the control sequencer instructs the first register to add the error mark, and outputs the image signal with the error mark to the recording unit and the image memory.
The register group includes a register for receiving an instruction to judge whether the decoding operation is continued until an end-of-page signal is received.
The code analyzer includes at least an analyzer sequencer responsive to a decoding instruction from the control sequencer, a code input unit for receiving the code signal in response to a shift instruction from the analyzer sequencer, a final signal detector for decoding a code signal representing an end-of-line, an analyzer table responsive to an operation instruction signal from the analyzer sequencer for receiving the code signal from the code input unit and analyzing the code signal, and an analyzing result latch for temporarily storing the analyzed code supplied from the analyzer table.
The analyzer sequencer includes at least a start instruction setting unit for setting a start of the decoding operation.
The transition point calculator includes at least a transition point address calculator sequencer responsive to an instruction signal from the control sequencer for outputting an operation instruction signal, an analyzed result latch responsive to the operation instruction signal from the calculator sequencer for latching the analyzed result, a decoded line transition point address calculator unit, a reference line access unit responsive to the operation instruction signal from the calculator sequencer for receiving the image signal of a reference line of one word from a reference line memory, and a transition point address detector for detecting a transition point address and outputting the transition point address, wherein an address of the transition point of the image signal on the decoded line is calculated from the analyzed result and the word address and bit address of the transition point.
The image signal recovering unit includes at least a recovery sequencer responsive to an instruction signal from the control sequencer, a decoded line transition point address input latch for receiving the decoded line transition address from the transition point calculator and outputting the decoded line transition address, and a line image signal generator unit for generating the image signal by changing pixels at the area from the address one point before the transition point address to the transition point address into ones of white pixels and black pixels and outputting the changed image signal to one of the line memories.
The transfer unit includes at least a transfer controller responsive to an instruction signal from the control sequencer for instructing to output the image signal in one of the image memories, a transfer memory controller responsive to an instruction signal from the transfer controller for accessing the one of the line memories, an error mark adding unit responsive to an error mark adding instruction signal from the transfer memory controller for adding an error mark of ones of white pixels and black pixels and outputting the image signal, and an image memory controller responsive to the instruction signal from the transfer controller for outputting an address and control signal for the image memory.
The encoding unit includes at least three line memories to be used cyclically as an image signal storage line, an encode line, and a reference line, and an encoding control unit for controlling the encoding operation one line after another, by always confirming that the image signal of at least one line is stored in the line memories, such that when the image signal of at least one line is stored in the line memories, the encoding operation of the image signal of one line starts by referencing the image signal on the reference line and at the same time the image signal to be next encoded is stored in the remaining line memory.
The encoding control unit includes at least an image signal input unit for receiving the image signal, a control sequencer for controlling the encoding operation, an encoding logic unit for encoding the image signal in accordance with one of an MH, MR, MMR, and run-length encoding schemes, a system interface unit for interfacing with an external system controller, and a code output unit for outputting the code signal supplied from the encoding logic unit.
The external system controller connected to the system interface unit executes necessary initial settings of encode registers provided in the encoding control unit and instructs to start the encoding operation.
The image input unit includes an image signal input controller for controlling the input of the image signal and a signal representing an end-of-page, and a line memory controller for receiving the image signal of one line and judging the contents of the image signal, the judgement including counting the number of the transition points and counting the number of black pixels.
The system interface includes the encode registers for setting various parameters required for the encoding operation, a control signal input/output unit for controlling data transfer between the system controller and the system interface unit, an interface control unit for interfacing between the system interface unit and the code signal output unit, the encode registers including a maximum value register for storing the maximum value of the transition points of one line, and the control signal input/output unit including a terminal for outputting an interrupt signal representing the interrupt of the encoding operation at one of encoded lines or at the end-of-page, to the system controller, and a terminal for setting one of an8-bit bus and a 16-bit bus.
The control sequencer instructs the encoding operation by one of the MH, MR and MMR encoding schemes when the number of counted transition points in a line of the image signal supplied to the line memories is greater than a predetermined value, and instructs the encoding operation by an uncompression encoding scheme when the number is greater than the value.
The control sequencer instructs the uncompression encoding scheme when the image signal supplied to the line memories conforms with one of a one-dimensional encoding scheme and a two-dimensional encoding scheme, in accordance with predetermined values set differently for the one-and two-dimensional encoding schemes.
The control sequencer includes a counter for counting the number of encoded lines of the image signal.
The encode registers include at least a register for setting the value of the number of encoded lines, a register for setting the configuration of the encoding operation, a register for setting the start position of the encoding operation from one of the page top position and the page intermediate position, and a register for setting one of the number of RTC codes for the MH and MR encoding schemes and the number of E of B codes for the MMR encoding scheme.
The encode registers further include a first register for setting a predetermined number of black pixels for determining that the image signal of one line is a black pixel line if the number of detected black pixels is greater than the predetermined number in which the image signal of one line is determined as a white line if the number of the black pixels is smaller than the predetermined number, and a second register for setting the number of consecutive black lines.
According to another aspect of the present invention, there is provided an information transmission/reception apparatus comprising: unit for reading an image and outputting an image signal of the image; encoding unit having a plurality of line memories for storing the image signal for encoding the image signal into a code signal while always confirming that the image signal of at least one line is stored in the line memories; unit for transmitting and receiving the code signal; decoding unit having a plurality of line memories for storing the image signal decoded by the code signal, the decoding unit decoding an input code signal from one of a page top position and a page intermediate position; and recording unit for recording the image signal decoded by the decoding unit.
If an original of one page has codes which cannot be recorded on one recording paper, the decoding is interrupted when codes of one recording paper have been decoded. After the next recording paper is set, the decoding starts from the next code. It is therefore possible to record an original of one page having codes unable to be recorded on one recording paper, on two recording papers in real time without using a page memory.
An end-of-page or end-of-block code is notified to the recorder when the code is decoded. The recorder therefore can record an original containing codes more than or less than one recording paper without using a page memory while decoding in real time.
A decoded image signal is outputted to both the recorder and the image memory. After transferring the image signal stored in the image memory, the newly decoded image signal is outputted to both the recorder and the image memory. It is therefore possible to record an original having codes more than one recording paper without using a page memory, and to record the same image signal on both the bottom portion of the first page and the top portion of the second page.
An error mark is added to the image signal of a line with an error and outputted to the recorder. It is therefore possible to record an error mark on a recording paper without using a page memory.
A maximum constant speed of inputting an image signal both in the main and subsidiary scan lines of a line sensor is ensured. If the image signal input speed is set slower than the maximum speed, the image signal input speed is not required to be controlled in accordance with the coding speed. It is therefore possible to simplify the system control. Since the image signal can be inputted at a constant speed, a buffer RAM between the recorder and the image signal processing apparatus is not necessary, reducing the cost.